DC Line Model: CHIGATT
AutoCorrection Properties
To be documented.
HVDC CHIGATT: Two terminal D.C. Transmission
This model has most of the same dynamic characteristics as CDC6T but with some modifications
• Auxiliary Signal Index 1 feeds into the MW schedule.
• Auxiliary Signal 2 feeds into the voltage signal.
• Input Parameter dVdI can be specified to change the slope of DC voltage/DC current characteristic as a transition between the full current and drop due to current margin is done. See the Bridge and Line Simulation Logic in the CDC6T help. dVdI represents the slope between points Y and X on that curve
• The voltage measurement used for the input to the VDCOL has 2 different time constants
o VDCOLUP is the time constant used when the voltage is increasing
o VDCOLDN is the time constant used when the voltage is decreasing
For a Detailed Treatment of how DC lines are implemented in the software see the help topic here.
Model supported by PSSE
Parameters:
| ALFDY | minimum alpha for dynamics (degrees) |
| GAMDY | minimum gamma for dynamics (degrees) |
| VDCOLUP | voltage transducer time constant up (sec) |
| TIDC | dc current transducer time constant (sec) |
| VDCOLDN | voltage transducer time constant down (sec) |
| VUNBL | rectifier ac unblocking voltage (pu) |
| TBLKBY | minimum blocking and bypassing time (sec) |
| dVdI | Inverter DeltaV/DeltaI slope characteristic (V/amps) |
| VUNBY | inverter ac unbypassing voltage (pu) |
| ACCL | model acceleration factor |
| RSVOLT | minimum dc voltage following block (kV) |
| RSCUR | minimum dc current following block (amps) |
| VRAMP | voltage recovery rate (pu/sec) |
| CRAMP | current recovery rate (pu/sec) |
| C0 | minimum current demand (amps) |
| V1 | voltage limit point 1 |
| C1 | current limit (amps); >= C0 |
| V2 | voltage limit point 2 |
| C2 | current limit point 2 (amps) |
| V3 | voltage limit point 3 |
| C3 | current limit point 3 (amps) |
| ALFMXI | maximum inverter firing angle (degrees) |
| VDEBLK | rectifier ac voltage that causes a block if remains for time TDEBLK (pu) |
| TDEBLK | time delay for block (sec) |
| TREBLK | time delay after rectifier ac voltage recovers above VUNBL before line unblocks (sec) |
| VINBLK | inverter ac voltage that causes block after communication delay TCOMB (pu) |
| TCOMB | communication delay to signal rectifier to block because of low inverter voltage (sec) |
| VACBYP | inverter ac voltage that causes bypass if remains for time TDEBYP (pu) |
| TDEBYP | time delay for bypass (sec) |
| TINBLK | time delay after inverter ac voltage recovers above VUNBY before line unblocks (this value should also include communication delay) (sec) |
| TINBYP | time delay after inverter ac voltage recovers above VUNBY before line unbypasses (sec) |
| TVP | power control VDC transducer time constant (sec) |